Reliable multilevel interconnect formation and metallization is paramount to the success of next generation ultra large scale integration (ULSI) devices and advanced packaging, including three-dimensional integration (3DI) of electronic devices and both tight-pitch solder bump and micro-bump technology. As an example, dual damascene copper (Cu) interconnect formed in high aspect ratio via, contacts, and lines is envisioned for extension to the 7 nm (nanometer) technology node for ULSI fabrication and beyond. Additionally, for example, metallized, through silicon via (TSV) structures with a diameter of 1 to 30 microns and a depth of 10 to 250 microns enable 3DI electronic devices, while mask patterned deposition of lead-free solder at tight pitch bumping, i.e., pitch less than 300 microns, or micro-bumping is contemplated for advanced packaging.
To enable the above technology, electroplating or electrochemical deposition (ECD), among other processes, is used as a manufacturing technique for the application of various materials, including metals such as tin (Sn), silver (Ag), Sn—Ag alloy, nickel (Ni), copper (Cu), or otherwise, to various structures and surfaces, such as semiconductor workpieces or substrates. An important feature of systems used for such processes is an ability to produce uniform and repeatable material properties, e.g., thickness, composition, mechanical or electrical characteristics, etc.